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E2E1037-19-41
Semiconductor MSM80C31F/MSM80C51F
Semiconductor CMOS 8-Bit Microcontroller
This version: Mar. 1995 MSM80C31F/80C51F
GENERAL DESCRIPTION
The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device has two software selectable modes for further power reduction -- Idle and Power Down. Idle mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers, serial port and interrupt system to continue functions. Power Down mode saves the RAM contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
* Low power consumption by 2 mm silicon gate CMOS process technology * Fully static circuit * Internal program memory : 4K bytes (MSM80C51F) www..com * External program memory space : 64K bytes * Internal data memory (RAM) : 128 bytes * External data memory (RAM) space : 64K bytes * I/O ports : 8-bit 4 ports * Two 16-bit timer/counters * Multifunctional serial port (UART) * Five interrupt sources (Priority can be set) * Four sets of working registers (R0-7 4) * Stack : Internal data memory (RAM) 128-byte area can be used arbitrarily (by SP specified) * Two CPU power-down modes (1) Idle mode : CPU stopped while oscillation continued. (Software setting) (2) PD mode : CPU and oscillation all stopped. (Software setting) (Setting I/O ports to floating status possible) * Operating temperature : -40 to +85C (@ 12 MHz, VCC = 5 V 20%) -20 to +70C (@ 16 MHz, VCC = 5 V 5%) * 2-byte 1-machine cycle instructions : 1 msec. @ 12 MHz 0.75 msec. @ 16 MHz * Multiplication/division instructions : 4 msec. @ 12 MHz 3 msec. @ 16 MHz * Instruction code addressing method Byte specification : Data addressing (direct) Bit specification : Bit addressing
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Semiconductor * Package options 40-pin plastic DIP (DIP40-P-600-2.54) : 44-pin plastic QFP (QFP44-P-910-0.80-2K) : 44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) :
MSM80C31F/80C51F
(MSM80C31F-RS) (MSM80C51F-RS) (MSM80C31F-GS) (MSM80C51F-GS) (MSM80C31F-JS) (MSM80C51F-JS) indicates the code number.
DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51
* Operating frequency 0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1 0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F * External clock input terminal XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1) XTAL2 ................................. MSM80C31/MSM80C51 * Emulation mode Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in MSM80C31F/MSM80C51F. Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for above three differences are the same as those of MSM80C31/MSM80C51.
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Semiconductor
BLOCK DIAGRAM
CONTROL
SIGNALS
R/W
SIGNALS
PORT 2
P2.0 to P2.7
ROM 4096 WORDS 8 BITS
PLA
SPECIAL FUNCTION REGISTER ADDRESS DECODER
ADDRESS DECODER
PCHL PORT 0 P0.0 to P0.7
PCLL
PCH XTAL1 PCON XTAL2 ALE PSEN EA RESET SP OSC AND TIMING PORT 1
PCL
SENSE AMP
IR
AIR C-ROM
DPH
DPL
R/W AMP ADDRESS DECODER
ACC
TR2
TR1
128 WORDS 8 BITS
RAMDP PSW ALU BR
P1.0 to P1.7
MSM80C31F/80C51F
TH1 PORT 3 P3.0 to P3.7
TL1
TH0 TIMER/COUNTER
TL0
TMOD
TCON
IE INTERRUPT
IP
SBUF(T)
SBUF(R) SERIAL IO
SCON
3/38
Basic Timing Chart
CLOCK WAVEFORMS
Semiconductor
CYCLE STEP XTAL1 ALE PSEN RD/WR PORT-0
1 0 1 0 1 0 1 0 S1 S2 S3
M1
S4 S5 S6 S1 S2 S3
M1
S4 S5 S6 S1 S2 S3
M2
S4 S5 S6 S1 S2 S3
M1
S4 S5 S6
DPL&Rr
1 0 1 0
PCL PCH PCH
PCL PCH DATA STABLE
,,, ,,, ,,, , ,,, ,,
PCL PCH
,,, ,,
ACC & RAM DPH & PORT DATA
,,, ,,,
PCL PCH
,,,
PCL PCH
PCL PCH
PORT-2
,,, ,,
DATA STABLE
,,, ,
,,, ,,, ,,
CPUPORT PORTCPU
1 0 1 0
,,, ,,
,
,,
PORT OLD DATA Instruction decoding Instruction execution PC+1 TM+1 PC+1
Port output/input Instruction execution
,, ,,
,,,
,,, ,,
,, ,,, ,,
,,, ,,
,,, ,,
,,, ,,
,,, ,,, ,
,,,
,,,
,,,
,,,
,,,
Instruction decoding Instruction execution PC+1 TM+1 TM+1
,,, ,,,
External data memory instruction execution Port output/input Instruction execution
,,, ,,, ,
,,,
,,,
PORT NEW DATA
,,,
,,,
,,,
,,,
,,,
,,,
,,
,,
,
Instruction decoding Instruction execution PC+1 TM+1 PC+1
,
MSM80C31F/80C51F
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Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW)
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET
1 2 3 4 5 6 7 8 9
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA ALE PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
RXD/P3.0 10 TXD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20
40-Pin Plastic DIP
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Semiconductor
PIN CONFIGURATION (TOP VIEW) (continued)
P1.5 P1.6 P1.7 RESET P3.0/RXD NC P3.1/TXD P3.2/INT0 P3.3/INT1
P3.4/T0 10 P3.5/T1/HPDI 11
,
44 P1.4 43 P1.3 42 P1.2 41 P1.1 40 P1.0 39 NC
1 2 3 4 5 6 7 8 9
MSM80C31F/80C51F
37 P0.0
36 P0.1
35 P0.2
34 P0.3
33 P0.4 32 P0.5 31 P0.6 30 P0.7 29 EA 28 NC 27 ALE 26 PSEN 25 P2.7 24 P2.6 23 P2.5
P3.6/WR 12
P3.7/RD 13
XTAL2 14
XTAL1 15
VSS 16
VSS 17
P2.0 18
38 VCC
P2.1 19
P2.2 20
P2.3 21
44-Pin Plastic QFP
P2.4 22
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Semiconductor
MSM80C31F/80C51F
PIN CONFIGURATION (TOP VIEW) (continued)
32 PSEN
39 P0.4
38 P0.5
37 P0.6
36 P0.7
31 P2.7
30 P2.6
P0.3 40 P0.2 41 P0.1 42 P0.0 43 VCC 44 NC 1 P1.0 2 P1.1 3 P1.2 4 P1.3 5 P1.4 6
29 P2.5
33 ALE
34 NC
35 EA
RESET 10 P3.0/RXD 11 NC 12 P3.1/TXD 13 P1.5 7 P1.6 8 P1.7 9
28 P2.4 27 P2.3 26 P2.2 25 P2.1 24 P2.0 23 NC 22 VSS 21 XTAL1 20 XTAL2 19 P3.7/RD 18 P3.6/WR
P3.2/INT0 14
P3.3/INT1 15
P3.4/T0 16
44-Pin Plastic QFJ (PLCC)
P3.5/T1 17
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Semiconductor
MSM80C31F/80C51F
PIN DESCRIPTION
Symbol VSS VCC Port 0.0 - 0.7 Port 1.0 - 1.7 Port 2.0 - 2.7 Port 3.0 - 3.7 Ground potential Supply voltage during Normal, Idle and Power Down operation Port 0 is an 8-bit open-drain bidirectional I/O port. It is also the mutiplexed low-order address and data bus during accesses to external memory. Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. It can drive CMOS inputs without external pull-ups. Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. It outputs the high-order address byte during accesses to external memory. It can drive CMOS inputs without external pull-ups. Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. It also provides various special features, as shown below: Alternate Function Port Pin (serial input port) RXD P3.0 (serial output port) TXD P3.1 (external interrupt) INT0 P3.2 (external interrupt) INT1 P3.3 (Timer 0 external input) T0 P3.4 (Timer 1 external input) T1 P3.5 (external data memory write strobe) WR P3.6 (external data memory read strobe) RD P3.7 Port 3 can drive CMOS inputs without external pull-ups. Reset input pin. A reset is accomplished by holding the RESET pin high for at least 1ms. even if the oscillator has been stopped. The CPU responds by executing an internal reset. An internal pull-down resistor permits Power-On reset using only a capacitor connected to VCC. This pin does not receive the power down voltage since the function has been transferred to the VCC pin. Address Latch Enable. This output latches for latching the low byte of the address during accesses to external memory. For this purpose, ALE is activated twice every machine cycle or at a constant rate of 1/6th the oscillator frequency, except during an external memory access at which time one ALE pulse is skipped. ALE can drive CMOS inputs without an external pull-up. PSEN Program Store Enable output. This output is the read strobe to external program memory. For this purpose, PSEN is activated twice every machine cycle. (However, when executing out of external program memory, two activations of PSEN are skipped during each access to external data memory.) PSEN is not activated during fetches from internal program memory. It can drive CMOS inputs without an external pull-up. External Access input pin. When EA is held high, the CPU executes out of internal program memory (unless the program counter exceeds 0FFFH). When EA is held low, the CPU executes only out of external program memory. EA must not be floated. XTAL1 XTAL2 Crystal 1 pin. It is an input to the inverting amplifier which forms the internal oscillator. Crystal 2 pin. It is an output of the inverting amplifier that forms the internal oscillator. Description
RESET
ALE
EA
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Semiconductor
MSM80C31F/80C51F
DATA MEMORY AND SPECIAL FUNCTION REGISTER LAYOUT DIAGRAM
0F0H 0E0H 0D0H 0B8H 0B0H 0A8H 0A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H
B ACC PSW IP P3 IE P2 SBUF SCON P1 TH1 TH0 TL1 TL0 TMOD TCON PCON DPH DPL SP P0
7F USER RAM 80W 8 bits 30 2F
DATA RAM
20 1F 18 17 10 0F 08 07 00
7F 78 BIT ADDRESSABLE RAM 7 0 R7 BANK 3 R0 R7 BANK 2 R0 R7 BANK 1 R0 R7 BANK 0 R0
SPECIAL FUNCTION REGISTERS
BIT ADDRESSING
DATA ADDRESSING
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Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF DATA MEMORY (RAM)
7FH 30H 2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH Bank 3 18H 17H Bank 2 10H 0FH Bank 1 08H 07H Bank 0 00H 0 8 7 16 15 24 23
REGISTER ADDRESSING
127 USER DATA RAM 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 48 47 46 45 44 43
BIT ADDRESSING INDIRECT ADDRESSING
42 41 40 39 38 37 36 35 34 33 32 31
DATA ADDRESSING
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Semiconductor
MSM80C31F/80C51F
DETAILED DIAGRAM OF SPECIAL FUNCITON REGISTERS
Special Function Register (LSB) Symbol F2 E2 OV D2 PX1 BA B2 EX1 AA A2 F1 E1 F1 D1 PT0 B9 B1 ET0 A9 A1 F0 E0 P D0 PX0 B8 B0 EX0 A8 A0 B ACC PSW IP P3 IE P2 SBUF TI 99 91 RI 98 90 SCON P1 TH1 TH0 TL1 TL0 TMOD IE0 89 IT0 88 TCON PCON DPH DPL SP 82 81 80 P0
Data Address 0F0H 0E0H 0D0H 0B8H 0B0H 0A8H 0A0H 99H 98H 90H 8DH 8CH 8BH 8AH 89H 88H 87H 83H 82H 81H 80H
(MSB) F7 E7 CY D7 -- B7 EA AF A7 F6 E6 AC D6 -- B6 -- A6 F5 E5 F0 D5 -- B5 -- A5
Bit Address F4 E4 RS1 D4 PS BC B4 ES AC A4 F3 E3 RS0 D3 PT1 BB B3 ET1 AB A3
SM0 9F 97
SM1 9E 96
Not Bit Addressable SM2 REN TB8 RB8 9D 9C 9B 9A 95 94 93 92
Not Bit Addressable Not Bit Addressable Not Bit Addressable Not Bit Addressable TF1 8F TR1 8E Not Bit Addressable TF0 TR0 IE1 IT1 8D 8C 8B 8A Not Bit Addressable Not Bit Addressable Not Bit Addressable Not Bit Addressable 87 86 85 84 83
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Semiconductor
MSM80C31F/80C51F
INSTRUCTION LIST
List of Instruction Symbols : : : : : : : : : : : : : : : : : : : : : : : AE : -- : < : > : bit address : code address : data : relative offset : direct address : A AB AC B C DPTR PC Rr SP AND OR XOR + - X / (X) ((X)) # @ = Accumulator Register pair Auxiliary carry flag Arithmetic operation register Carry flag Data pointer Program counter Register indicator (r = 0 to 7) Stack pointer Logical product Logical sum Exclusive-OR Addition Subtraction Multiplication Division Denotes the contents of X Denotes the contents of address determined by the contents of X Denotes the immediate data Denotes the indirect address Equality Non-equality Substitution Substitution Negation Smaller than Larger than RAM and the special function register bit specifier address (b0 to b7) Absolute address (A0 to A15) Immediate data (I0 to I7) Relative jump address offset value (R0 to R7) RAM and the special function register byte specifier address (a0 to a7)
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Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes
L H
0 0000 NOP
1 0001
2 0010 LJMP address 16 LCALL adress 16 RET RETI ORL direct, A ANL direct, A XRL direct, A ORL C, bit ANL C, bit MOV bit, C MOV C, bit CPL bit CLR bit SETB bit MOVX A, @R0 MOVX @R0, A
3 0011 RR A RRC A RL A RLC A ORL direct, #data ANL direct, #data XRL direct, #data JMP @A+DPTR MOVC A, @A+PC MOVC A, @A+DPTR INC DPTR CPL C CLR C SETB C MOVX A, @R1 MOVX @R1, A
4 0100 INC A DEC A ADD A, #data ADDC A, #data ORL A, #data ANL A, #data XRL A, #data MOV A, #data DIV AB SUBB A, #data MUL AB CJNE A, #data rel SWAP A DA A CLR A CPL A
5 0101 INC direct DEC direct ADD A, direct ADDC A, direct ORL A, direct ANL A, direct XRL A, direct MOV direct #data MOV direct1, direct2 SUBB A, direct
6 0110 INC @R0 DEC @R0 ADD A, @R0 ADDC A, @R0 ORL A, @R0 ANL A, @R0 XRL A, @R0
7 0111 INC @R1 DEC @R1 ADD A, @R1 ADDC A, @R1 ORL A, @R1 ANL A, @R1 XRL A, @R1
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
AJMP address 11 (Page 0) ACALL JBC bit, address 11 rel (Page 0) AJMP JB bit, address 11 rel (Page 1) ACALL JNB bit, address 11 rel (Page 1) AJMP JC address 11 rel (Page 2) ACALL JNC rel address 11 (Page 2) AJMP JZ rel address 11 (Page 3) ACALL JNZ rel address 11 (Page 3) AJMP SJMP rel address 11 (Page 4) ACALL MOV DPTR, address 11 #data 16 (Page 4) AJMP ORL C, /bit address 11 (Page 5) ACALL ANL C, /bit address 11 (Page 5) AJMP PUSH address 11 direct (Page 6) ACALL POP address 11 direct (Page 6) AJMP MOVX A, address 11 @DPTR (Page 7) ACALL MOVX address 11 @DPTR, A (Page 7)
MOV @R0, MOV @R1, #data #data MOV direct, @R0 SUBB A, @R0 MOV direct, @R1 SUBB A, direct
MOV @R0, MOV @R1, direct direct CJNE A, direct, rel XCH A, direct DJNZ direct, rel MOV A, direct MOV direct, A CJNE @R0 CJNE @R1, #data, #data, rel rel XCH A, @R0 XCHD A, @R0 MOV A, @R0 MOV @R0, A XCH A, @R1 XCHD A, @R1 MOV A, @R1 MOV @R1, A
2BYTES MNEMONIC 2CYCLES
3BYTES 4CYCLES
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Semiconductor
MSM80C31F/80C51F
MSM80C31F/MSM80C51F Instruction Codes (continued)
L H 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 8 1000 INC R0 DEC R0 9 1001 INC R1 DEC R1 A 1010 INC R2 DEC R2 B 1011 INC R3 DEC R3 C 1100 INC R4 DEC R4 D 1101 INC R5 DEC R5 E 1110 INC R6 DEC R6 F 1111 INC R7 DEC R7
ADD A, R0 ADD A, R1 ADD A, R2 ADD A, R3 ADD A, R4 ADD A, R5 ADD A, R6 ADD A, R7 ADDC A, R0 ADDC A, R1 ADDC A, R2 ADDC A, R3 ADDC A, R4 ADDC A, R5 ADDC A, R6 ADDC A, R7 ORL A, R0 ORL A, R1 ORL A, R2 ORL A, R3 ORL A, R4 ORL A, R5 ORL A, R6 ORL A, R7 ANL A, R0 XRL A, R0 MOV R0, #data MOV direct, R0 SUBB A, R0 MOV R0, direct CJNE R0, #data rel XCH A, R0 DJNZ R0, rel ANL A, R1 XRL A, R1 MOV R1, #data MOV direct, R1 SUBB A, R1 MOV R1, direct CJNE R1, #data rel XCH A, R1 DJNZ R1, rel ANL A, R2 XRL A, R2 MOV R2, #data MOV direct, R2 SUBB A, R2 MOV R2, direct CJNE R2, #data rel XCH A, R2 DJNZ R2, rel ANL A, R3 XRL A, R3 MOV R3, #data MOV direct, R3 SUBB A, R3 MOV R3, direct CJNE R3, #data rel XCH A, R3 DJNZ R3, rel ANL A, R4 XRL A, R4 MOV R4, #data MOV direct, R4 SUBB A, R4 MOV R4, direct CJNE R4, #data rel XCH A, R4 DJNZ R4, rel ANL A, R5 XRL A, R5 MOV R5, #data MOV direct, R5 SUBB A, R5 MOV R5, direct CJNE R5, #data rel XCH A, R5 DJNE R5, rel ANL A, R6 XRL A, R6 MOV R6, #data MOV direct, R6 SUBB A, R6 MOV R6, direct CJNE R6, #data rel XCH A, R6 DJNE R6, rel ANL A, R7 XRL A, R7 MOV R7, #data MOV direct, R7 SUBB A, R7 MOV R7, direct CJNE R7, #data rel XCH A, R7 DJNE R7, rel
MOV A, R0 MOV A, R1 MOV A, R2 MOV A, R3 MOV A, R4 MOV A, R5 MOV A, R6 MOV A, R7 MOV R0, A MOV R1, A MOV R2, A MOV R3, A MOV R4, A MOV R5, A MOV R6, A MOV R7, A
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Semiconductor
MSM80C31F/80C51F
Instruction Set Details
Type Mnemonic ADD A, Rr ADD A, direct ADD A, @Rr ADD A, #data ADDC A, Rr ADDC A, direct ADDC A, @Rr Airthmetic operation instructions ADDC A, #data SUBB A, Rr SUBB A, direct SUBB A, @Rr SUBB A, #data MUL AB DIV AB DA A Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 I7 0 0 0 0 I7 1 1 1 1 I7 1 1 1 0 0 0 0 I6 0 0 0 0 I6 0 0 0 0 I6 0 0 1 1 1 1 1 I5 1 1 1 1 I5 0 0 0 0 I5 1 0 0 0 0 0 0 I4 1 1 1 1 I4 1 1 1 1 I4 0 0 1 1 0 0 0 I3 1 0 0 0 I3 1 0 0 0 I3 0 0 0 r2 1 1 1 I2 r2 1 1 1 I2 r2 1 1 1 I2 1 1 1 r1 0 1 0 I1 r1 0 1 0 I1 r1 0 1 0 I1 0 0 0 r0 1 r0 0 I0 r0 1 r0 0 I0 r0 1 r0 0 I0 0 0 0 1 1 1 4 4 1 1 2 1 2 1 1 1 1 (AC), (0V), (C), (A) (A)-((C))+((Rr)) (AC), (0V), (C), (A) (A)-((C)+ (direct address)) (AC), (0V), (C), (A) (A)-((C)+((Rr)) (AC), (0V), (C), (A) (A)-((C)+ #data) (AB) (A) x (B) (A)quotient, (B) remainder (A)/(B) 1 2 1 2 1 1 1 1 (AC), (0V), (C), (A) (A)+(C)+(Rr) (AC), (0V), (C), (A) (A)+(C)+ (direct address) (AC), (0V), (C), (A) (A)+(C)+((Rr)) (AC), (0V), (C), (A) (A)+(C)+#data Bytes Cycles 1 2 1 2 1 1 1 1 Description (AC), (0V), (C), (A) (A)+(Rr) (AC), (0V), (C), (A) (A)+(direct address) (AC), (0V), (C), (A) (A)+((Rr)) (AC), (0V), (C), (A) (A)+#data
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4
a3 a2 a1 a0
When the contents of accumulator bits 0 thru 3 are greater than 9, or when auxiliary carry (AC) is 1, 6 is added to bits 0 thru 3. Bits 4 thru 7 are then examined, and when bits 4thru 7 follwoing compensation of lower bits 0 thru 3 is greater than 9, or when carry (C) is 1, 6 is added to bits 4 thru 7. As a result, the cary flag can be set, but cannot be cleared. (A) 0 (A) (A)
C
CLR A Accumulation operation instructions CPL A PL A
1 1 0
1 1 0
1 1 1
0 1 0
0 0 0
1 1 0
0 0 1
0 0 1
1 1 1
1 1 1
Accumulator 7 0 Accumulator 7 0
PL C
0
0
1
1
0
0
1
1
1
1
C
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Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic RR A Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 1 1 Bytes Cycles 1 1
C
Description Accumulator AEAEAEAEAEAEAEAE 7 0 Accumulator AEAEAEAEAEAEAEAE 7 0
Accumulation operation instructions
RRC A
0
0
0
1
0
0
1
1
1
1
C
SWAP A INC A INC Rr INC direct INC @Rr INC DPTR DEC A DEC Rr DEC direct DEC @Rr ANL A, Rr ANL A, direct ANL A, @Rr ANL A, #data
1 0 0 0 0 1 0 0 0 0 0 0 0 0 I7 0 0 I7
1 0 0 0 0 0 0 0 0 0 1 1 1 1 I6 1 1 I6 1 1 1 1 I6 1
0 0 0 0 0 1 0 0 0 0 0 0 0 0 I5 0 0 I5 0 0 0 0 I5 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 I4 1 1 I4 0 0 0 0 I4 0
0 0 1 0 0 0 0 1 0 0 1 0 0 0 I3 0 0 I3 1 0 0 0 I3 0
1 1 r2 1 1 0 1 r2 1 1 r2 1 1 1 I2 0 0 I2 r2 1 1 1 I2 0
0 0 r1 0 1 1 0 r1 0 1 r1 0 1 0 I1 1 1 I1 r1 0 1 0 I1 1
0 0 r0 1 r0 1 0 r0 1 r0 r0 1 r0 0 I0 0 1 I0 r0 1 r0 0 I0 0
1 1 1 2 1 1 1 1 2 1 1 2 1 2 2 3
1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 2
(A4 -7) (A0 -3) (A) (A)+1 (Rr) (Rr)+1 (direct address) (direct address)+1 ((Rr)) ((Rr))+1 (DPTR) (DPTR)+1 (A) (A)-1 (Rr) (Rr)-1 (direct address) (direct address)-1 ((Rr)) ((Rr))-1 (A) (A) AND (Rr) (A) (A) AND (direct address) (A) (A) AND ((Rr)) (A) (A) AND #data (direct address) (direct address) AND (A) (direct address) (direct address) AND #data
Increment/decrement
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4
a3 a2 a1 a0
Logical operation instructions
ANL direct, A ANL direct, #data
a7 a6 a5 a4 a7 a6 a5 a4 0 0 0 0 I7 ORL direct, A 0
a3 a2 a1 a0 a3 a2 a1 a0 1 2 1 2 2 1 1 1 1 1
ORL A, Rr ORL A, direct ORL A, @Rr ORL A, #data
(A) (A) OR (Rr) (A) (A) OR (direct address) (A) (A) OR ((Rr)) (A) (A) OR #data (direct address) (direct address) OR (A)
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4
a3 a2 a1 a0
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Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic ORL direct, #data Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 I7 1 I6 1 1 1 1 I6 1 1 I6 1 I6 1 I6 1 I6 1 I6 0 I6 1 1 0 0 0 1 0 0 I5 1 1 1 1 I5 1 1 I5 1 I5 1 I5 1 I5 1 I5 0 I5 0 0 1 0 1 1 1 0 I4 0 0 0 0 I4 0 0 I4 1 I4 1 I4 1 I4 1 I4 1 I4 0 1 1 0 1 1 0 0 I3 1 0 0 0 I3 0 0 I3 0 I3 1 I3 0 I3 0 I3 0 I3 0 0 0 0 0 0 0 0 I2 r2 1 1 1 I2 0 0 I2 1 I2 r2 I2 1 I2 1 I2 0 I2 0 0 0 0 0 0 0 1 I1 r1 0 1 0 I1 1 1 I1 0 I1 r1 I1 0 I1 1 I1 0 I1 1 1 1 1 0 1 0 1 I0 r0 1 r0 0 I0 0 1 I0 0 I0 r0 I0 1 I0 r0 I0 0 I8 I0 1 1 1 0 0 0 0 1 1 1 2 2 2 2 1 1 1 2 2 2 2 (C) 0 (C) 1 (C) (C) (C) (C) AND (bit address) (C) (C) AND (bit address) (C) (C) OR (bit address) (C) (C) OR (bit address) 3 2 (DPTR) #data 16 2 1 (Rr)) #data 3 2 (direct address) #data 2 1 (Rr) #data 2 1 (A) #data 2 3 1 2 (direct address) (direct address) XOR (A) (direct address) (direct address) XOR #data 1 2 1 2 1 1 1 1 (A) (A) XOR (Rr) (A) (A) XOR (direct address) (A) (A) XOR ((Rr)) (A) (A) XOR #data a7 a6 a5 a4 0 0 0 0 I7 XRL direct, A XRL direct, #data 0 0 I7 MOV A, #data 0 I7 MOV Rr, #data MOV direct, #data 0 I7 0 I7 MOV @Rr, #data MOV DPTR, #data 16 0 I7 1 I7 CLR C 1 1 1 1 1 0 1 a3 a2 a1 a0 Bytes Cycles 3 2 Description (direct address) (direct address) OR #data
Logical operation instructions
XRL A, Rr XRL A, direct XRL A, @Rr XRL A, #data
a7 a6 a5 a4
a3 a2 a1 a0
a7 a6 a5 a4 a7 a6 a5 a4
a3 a2 a1 a0 a3 a2 a1 a0
Immediate data setting instructions
a7 a6 a5 a4
a3 a2 a1 a0
I15 I14 I13 I12 I11 I10 I9
Carry flag operation instructions
SETB C CPL C ANL C, bit ANL C,/bit ORL C, bit ORL C,/bit
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
17/38
Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic MOV C, bit MOV bit, C SETB bit Instruction code D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 1 1 1
2 a7 1 a7
Bytes Cycles 2 2 2 2 2 1 2 1 1 2 2 2 3 1 2 1 1 1 1 1 1 1 2 1 2 2
Description (C) (bit address) (bit address) (C) (bit address) 1 (bit address) 0 (bit address) (bit address) (A) (Rr) (A) (direct address) (A) ((Rr)) (Rr) (A) (Rr) (direct address) (direct address) (A) (direct address) (Rr) (direct address 1) (direct address 2)
Carry flag operation instructions
0 0 1 1 0 1 1 1 1 0 1 0 0
2 a6 1 a6
1 0 0 0 1 1 1 1 1 1 1 0 0
2 a5 1 a5
0 1 1 0 1 0 0 0 1 0 1 0 0
2 a4 1 a4
0 0 0 0 0 1 0 0 1 1 0 1 0
2 a3 1 a3
0 0 0 0 0 r2 1 1 r2 r2 1 r2 1
2 a2 1 a2
1 1 1 1 1 r1 0 1 r1 r1 0 r1 1
2 a1 1 a1
0 0 0 0 0 r0 1 r0 r0 r0 1 r0 r0
2 a0 1 a0
b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 CLR bit CPL bit MOV A, Rr MOV A, direct MOV A, @Rr MOV Rr, A b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0
Bit operation instructions
a7 a6 a5 a4
a3 a2 a1 a0
Data transfer instructions
MOV Rr, direct MOV direct, A MOV direct, Rr MOV direct 1, direct 2
a7 a6 a5 a4 a7 a6 a5 a4 a7 a6 a5 a4
a3 a2 a1 a0 a3 a2 a1 a0 a3 a2 a1 a0
MOV @Rr, A MOV @Rr, direct
1 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 1 0 0 0 0 0 0
1 0 1 0 0 0 0 1
0 0 0 0 1 0 0 0
1 1 0 0 r2 1 1 1
1 1 1 1 r1 0 1 1
r0 r0 1 1 r0 1 r0 r0
1 2 1 1 1 2 1 1
1 2 2 2 1 2 1 1
((Rr)) (A) ((Rr)) (direct address) (A) ((A)+(DPTR)) (PC) (PC+1) (A) ((A)+(PC)) (A) (Rr) (A) (direct address) (A) ((Rr)) (A0 - 3) ((Rr0 - 3))
a7 a6 a5 a4
a3 a2 a1 a0
Constant code instructions Data exchange instructions
MOVC A, @A+DPTR MOVC A, @A+PC XCH A, Rr XCH A, direct XCH A, @Rr XCHD A, @Rr
a7 a6 a5 a4
a3 a2 a1 a0
18/38
Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic PUSH direct POP direct ACALL addr 11 Instruction code D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 a7 a6 a5 a4 a7 a6 a5 a4 A10 A9 A8 a3 a2 a1 a0 2 2 2 2 a3 a2 a1 a0 Bytes Cycles 2 2 Description (SP) (SP)+1 ((SP)) (direct address) (direct address) ((SP)) (SP) (SP)-1 (PC) (PC)+2 (SP) (SP)+1 ((SP)) (PC0 - 7) (SP) (SP)+1 ((SP)) (PC8 - 15) (PC0 - 10) A0 - 10 (PC) (PC)+3 (SP) (SP)+1 ((SP)) (PC0 - 7) (SP) (SP)+1 ((SP)) (PC8 - 15) (PC0 - 10) A0 - 10 (PC8 - 15) ((SP)) (SP) (SP)-1 (PC0 - 7) ((SP)) (SP) (SP)-1 (PC8 - 15) ((SP)) (SP) (SP)-1 (PC0 - 7) ((SP)) (SP) (SP)-1 (PC) (PC)+2 (PC0 - 10) A0 - 10 (PC0 - 15) A0 - 15
A7 A6 A5 A4 A3 A2 A1 A0
Subroutine instructions
LCALL addr 16
0
0
0
1
0
0
1
0
3
2
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
RET
0
0
1
0
0
0
1
0
1
2
RETI
0
0
1
1
0
0
1
0
1
2
AJMP addr 11
A10 A9 A8 0 0 0
0 0
0 0
0 0
0 1
1 0
2 3
2 2
Jump instructions
A7 A6 A5 A4 A3 A2 A1 A0 LJMP addr 16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SJMP rel JMP @A+ DPTR 1 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 2 1 2 2 R7 R6 R5 R4 R3 R2 R1 R0
(PC) (PC)+3 (SP) (SP)+1 (PC) (A)+(DPTR)
19/38
Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 a3 a2 a1 a0 Bytes Cycles 3 2 Description (PC) (PC)+3 IF (A)(direct address) THEN (PC) (PC)+relative offset IF (A)<(direct address) THEN (C) 1 ELSE (C) 0 (PC) (PC)+3 IF (A) #data THEN (PC) (PC)+relative offset IF (A)< #data THEN (C) 1 ELSE (C) 0 (PC) (PC)+3 IF ((Rr)) #data THEN (PC) (PC)+relative offset IF (Rr))< #data THEN (C) 1 ELSE (C) 0 (PC) (PC)+3 IF ((Rr)) #data THEN (PC) (PC)+relative offset IF ((Rr))< #data THEN (C) 1 ELSE (C) 0 (PC) (PC)+2 (Rr) (Rr)-1 IF (Rr)< 0 THEN (PC) (PC)+relative offset (PC) (PC)+3 (direct address) (direct address)-1 IF (direct address) 0 THEN (PC) (PC)+relative offset
CJNE A, direct, 1 0 1 1 rel a7 a6 a5 a4
R7 R6 R5 R4 R3 R2 R1 R0
CJNE A, #data, rel
1 I7
0 I6
1 I5
1 I4
0 I3
1 I2
0 I1
0 I0
3
2
R7 R6 R5 R4 R3 R2 R1 R0
Branch instructions
CJNE Rr, #data, rel
1 I7
0 I6
1 I5
1 I4
1 I3
r2 I2
r1 I1
r0 I0
3
2
R7 R6 R5 R4 R3 R2 R1 R0
CJNE @Rr, #data, rel
1 I7
0 I6
1 I5
1 I4
0 I3
1 I2
1 I1
r0 I0
3
2
R7 R6 R5 R4 R3 R2 R1 R0
DJNZ Rr, rel
1
1
0
1
1
r2
r1
r0
2
2
R7 R6 R5 R4 R3 R2 R1 R0
DJNZ direct, rel
1
1
0
1
0
1
0
1
3
2
a7 a6 a5 a4
a3 a2 a1 a0
R7 R6 R5 R4 R3 R2 R1 R0
20/38
Semiconductor
MSM80C31F/80C51F
Instruction Set Details (continued)
Type Mnemonic JZ rel Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 0 0 0 0 R7 R6 R5 R4 R3 R2 R1 R0 JNZ rel 0 1 1 1 0 0 0 0 2 2 Bytes Cycles 2 2 Description (PC) (PC)+2 IF (A) = 0 THEN (PC) (PC)+relative offset (PC) (PC)+2 IF (A) 0 THEN (PC) (PC)+relative offset (PC) (PC)+2 IF (C) = 1 THEN (PC) (PC)+relative offset (PC) (PC)+2 IF (C) = 0 THEN (PC) (PC)+relative offset (PC) (PC)+3 IF (bit address) = 1 THEN (PC) (PC)+relative offset (PC) (PC)+3 IF (bit address) = 0 THEN (PC) (PC)+relative offset (PC) (PC)+3 IF (bit address) = 1 THEN (bit address) 0 (PC) (PC)+relative offset (A) ((Rr)) EXTERNAL RAM (A) ((DPTR)) EXTERNAL RAM (Rr) (A) EXTERNAL RAM ((DPTP)) (A) EXTERNAL RAM (PC) (PC)+1
R7 R6 R5 R4 R3 R2 R1 R0 JC rel 0 1 0 0 0 0 0 0 2 2
R7 R6 R5 R4 R3 R2 R1 R0
Branch instructions
JNC rel
0
1
0
1
0
0
0
0
2
2
R7 R6 R5 R4 R3 R2 R1 R0 JB bit, rel 0 0 1 0 0 0 0 0 3 2
b7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 JNB bit, rel 0 0 1 1 0 0 0 0 3 2 b7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 JBC bit, rel 0 0 0 1 0 0 0 0 3 2 b7 b6 b5 b4 b3 b2 b1 b0 R7 R6 R5 R4 R3 R2 R1 R0 MOVX A, @Rr 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 r0 0 r0 0 0 1 1 1 1 1 2 2 2 2 1
External memory instructions Other instructions
MOVX A, @DPTR MOVX @Rr, A MOVX @DPTR, A NOP
21/38
Semiconductor
MSM80C31F/80C51F
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Voltage from Any Pin to VSS Storage Temperature Symbol VCC VI TSTG Condition Ta = 25C Ta = 25C -- Rating -0.5 to +7.0 -0.5 to VCC +7.0 -55 to +150 Unit V V C
OPERATING RANGE
Parameter Supply Voltage Memory Retention Voltage Oscillation Frequency Ambient Temperature Symbol VCC VCC fOSC Ta Condition See figure below fOSC = Oscillation stop See figure below MSM80C31F/51F MSM80C31F-1 Range 2.5 to 6 2 to 6 DC to 16 -40 to +85 -20 to +70 *2 *1 Unit V V MHz C
*1 DC & AC characteristics in the range of 2.5 V VCC < 4 V will be specified by DC & AC Characteristics 2. *2 Specify MSM80C31F-1 when using MSM80C31F at 12 MHz to 16 MHz.
GUARANTEED OPERATING RANGE
Ta = -40 to +85C (MSM80C31F/80C51F) Ta = -20 to +70C (MSM80C31F-1) 1.2
[ms] 10
4 Cycle Time (tcy) 3 2 MSM80C31/51 MSM80C31F/51F 1 0.75 MSM80C31F-1 2 3 4 Supply Voltage (VCC) 5 6 [V] 12 16 Operating Range 6
Oscillation Frequency (fOSC)
5
3
22/38
Semiconductor
MSM80C31F/80C51F
ELECTRICAL CHARACTERISTICS
DC Characteristics 1
MSM80C31F/51F VCC = 5 V 20%, VSS = 0 V, Ta = -40C to +85C MSM80C31F-1/51F-1 VCC = 5 V 5%, VSS = 0 V, Ta = -20C to +70C MeasSymbol Condition Min. Typ. Max. Unit uring circuit VIL VIH VIH1 VOL VOL1 -- Except XTAL1, RESET and EA XTAL1, RESET and EA IOL = 1.6 mA IOL = 3.2 mA IOH = -60 mA High Output Voltage (Port 1, 2 and 3) VOH VCC = 5 V 10% IOH = -30 mA IOH = -10 mA IOH = -400 mA High Output Voltage (Port 0, ALE and PSEN) Output Current at Low Input/ High Output Power Supply Output Current (Port 1, 2 and 3) at transition from H to L Input Leakage Current (Floating Port 0 and EA) RESET Pull-down Resistor Input Pin Capacitor Power Down Current VOH1 VCC = 5 V 10% IOH = -150 mA IOH = -40 mA IIL / IOH ITL ILI RRST CIO IPD VI = 0.45 V VO = 0.45 V VIL = 2.0 V VSS < VI < VCC -- Ta = 25C, f = 1 MHz 5 V (except XTAL1) VCC = 2 V -0.5 0.2 VCC + 0.9 0.7 VCC -- -- 2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -10 -- -- 20 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 40 -- 1 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45 -- -- -- -- -- -- -200 -500 10 125 10 50 V V V V V 1 V V V V V V mA 2 mA mA kW pF mA 3 2 -- 4
Parameter Low Input Voltage High Input Voltage High Input Voltage Low Output Voltage (Port 1, 2 and 3) Low Output Voltage (Port 0, ALE and PSEN)
23/38
Semiconductor
MSM80C31F/80C51F
DC Characteristics 2
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -40 to +85C) MeasMin. Typ. Max. Unit uring circuit -0.5 -- 0.25VCC - 0.1 VCC + 0.5 VCC + 0.5 0.1 0.1 -- -- -100 -300 10 125 10 10 V V V V 1 VOL1 VOH VOH1 IIL / IOH ITL ILI RRST CIO IPD IOL = 20 mA IOH = -5 mA IOH = -20 mA VI = 0.1 V VO = 0.1 V VIL = 1.9 V VSS < VI < VCC -- Ta = 25C, f = 1 MHz 5 V (except XTAL1) -- -- 0.75 VCC 0.75 VCC -- -- -- 20 -- -- -- -- -- -- -- -- 40 -- 1 V V V mA 2 mA mA kW pF mA 3 2 -- 4
Parameter Low Input Voltage High Input Voltage High Input Voltage Low Output Voltage (Port 1, 2 and 3) Low Output Voltage (Port 0, ALE and PSEN) High Output Voltage (Port 1, 2 and 3) High Output Voltage (Port 0, ALE and PSEN) Output Current at Low Input/ High Output Power Supply Output Current (Port 1, 2 and 3) at transition from H to L Input Leakage Current (Floating Port 0 and EA) RESET Pull-down Resistor Input Pin Capacitor Power Down Current
Symbol VIL VIH VIH1 VOL
Condition -- Except XTAL1, RESET and EA
0.25VCC + 0.9 -- -- --
XTAL1, RESET and EA 0.6VCC + 0.6 IOL = 10 mA --
24/38
Semiconductor Maximum operating power supply ICC [mA]
VCC Freq 0.5 MHz 3.0 MHz 8 MHz 12 MHz 0.7 1.9 -- -- 0.9 2.4 -- -- 1.6 4.3 8.3 12.0 2.5 V 3.0 V 4.0 V
MSM80C31F/80C51F
Maximum IDLE power supply ICC [mA]
VCC Freq 0.5 MHz 3.0 MHz 8 MHz 12 MHz 0.3 0.6 -- -- 0.4 0.8 -- -- 0.6 1.2 2.2 3.1 2.5 V 3.0 V 4.0 V
25/38
Semiconductor Measuring Circuit
1 2
MSM80C31F/80C51F
VCC
OUTPUT INPUT
(*2) A IO
(*1)
INPUT
VCC
OUTPUT
VIH VIL
(*3)
V
VA
VSS
VSS
3
4 A
VCC
OUTPUT INPUT
(*2) (*3) VIL
INPUT
VCC VIH
OUTPUT
VIH (*3) VIL
V
A
VSS
VSS
*1 Repeated for specified input pin. *2 Repeated for specified output pin. *3 Logic input for specified condition.
26/38
Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 1 (VCC = 5 V 20%, VSS = 0 V, Ta = -40C to +85C; Load Capacitance for Port 0, ALE, and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock Parameter Symbol 12 MHz Clock Min. XTAL1, XTAL2 Oscillation Cycle ALE Signal Width Adderss Setup Time (to ALE Falling Edge) Adderss Hold Time (from ALE Falling Edge) Instruction Data Read Time (from ALE Falling Edge) From ALE Falling Edge to PSEN Falling Edge PSEN Signal Width Instruction Data Read Time (from PSEN Falling Edge) Instruction Data Hold Time (from PSEN Rising Edge) Bus Floating Time after Instruction Data Read (from PSEN Rising Edge) Address Output Time from PSEN Rising Edge Instruction Data Read Time (from Address Output) Bus Floating Time (Address Float from PSEN Falling Edge) tPLAZ -- 0 -- 0 ns tAVIV -- 312 -- 5tCLCL - 105 ns tPXAV 75 -- 1tCLCL - 8 -- ns tPXIZ -- 63 -- 1tCLCL - 20 ns tPXIX 0 -- 0 -- ns tPLPH tPLIV 215 -- -- 145 3tCLCL - 35 -- -- 3tCLCL - 105 ns ns tLLPL 58 -- 1tCLCL - 25 -- ns tLLIV -- 233 -- 4tCLCL - 100 ns tLLAX 48 -- 1tCLCL - 35 -- ns tCLCL tLHLL tAVLL -- 126 43 Max. -- -- -- See Guaranteed Operating Range Min. 83.3 2tCLCL - 40 1tCLCL - 40 Max. -- -- -- ns ns ns Unit
27/38
Semiconductor
MSM80C31F/80C51F
External Program Memory Access AC Characteristics 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -40C to +85C; Load Capacitance for Port 0, ALE, and PSEN = 100 pF ; Load Capacitance for all other outputs = 80 pF)
Variable Clock Parameter Symbol 12 MHz Clock Min. XTAL1, XTAL2 Oscillation Cycle ALE Signal Width Adderss Setup Time (to ALE Falling Edge) Adderss Hold Time (from ALE Falling Edge) Instruction Data Read Time (from ALE Falling Edge) From ALE Falling Edge to PSEN Falling Edge PSEN Signal Width Instruction Data Read Time (from PSEN Falling Edge) Instruction Data Hold Time (from PSEN Rising Edge) Bus Floating Time after Instruction Data Read (from PSEN Rising Edge) Address Output Time from PSEN Rising Edge Instruction Data Read Time (from Address Output) Bus Floating Time (Address Float from PSEN Falling Edge) tPLAZ -- 0 -- 0 ns tAVIV -- 312 -- 5tCLCL - 105 ns tPXAV 75 -- 1tCLCL - 8 -- ns tPXIZ -- 63 -- 1tCLCL - 20 ns tPXIX 0 -- 0 -- ns tPLPH tPLIV 215 -- -- 145 3tCLCL - 35 -- -- 3tCLCL - 105 ns ns tLLPL 58 -- 1tCLCL - 25 -- ns tLLIV -- 233 -- 4tCLCL - 100 ns tLLAX 48 -- 1tCLCL - 35 -- ns tCLCL tLHLL tAVLL -- 126 43 Max. -- -- -- See Guaranteed Operating Range Min. 83.3 2tCLCL - 40 1tCLCL - 40 Max. -- -- -- ns ns ns Unit
28/38
Semiconductor
MSM80C31F/80C51F
External Program Memory Read Cycle
tLHLL
ALE
tAVLL
tLLPL tLLIV
tPLPH
tPLIV PSEN tPXAV tPXIZ tLLAX tPLAZ tPXIX
PORT0
A0~A7
INSTR IN
A0~A7
tAVIV
PORT2
A8~A15
A8~A15
A8~A15
29/38
Semiconductor External Data Memory Access AC Characteristics 1
MSM80C31F/80C51F
(VCC = 5 V 20%, VSS = 0 V, Ta = -40C to +85C; load capacitance for Port 0, ALE, and PSEN = 100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock Parameter Symbol 12 MHz Clock Min. XTAL1, XTAL2 Oscillation Cycle ALE Single Width Adderss Setup Time (to ALE Falling Edge) Adderss Hold Time (from ALE Falling Edge) RD Single Width WR Single Width RAM Data Read Time (from RD Single Falling Edge) RAM Data Read Hold Time (from RD Single Rising Edge) Data Bus Floating Time (from RD Single Rising Edge) RAM Data Read Time (from ALE Single Falling Edge) RAM Data Read Time (from Address Output) RD/WR Output Time from ALE Falling Edge RD/WR Output Time from Address Output RD Output Time from Data Output Time from Data Output to WR Rising Edge Data Hold Time (WR Rising Edge) Time from RD Output to Address Float Time from RD/WR Rising Edge to ALE Rising Edge tWHLH 43 133 1tCLCL - 40 1tCLCL + 50 ns tWHQX tRLAZ 33 -- -- 0 1tCLCL - 50 -- -- 0 ns ns tQVWX tQVWH 23 433 -- -- 1tCLCL - 60 7tCLCL - 150 -- -- ns ns tAVWL 203 -- 4tCLCL - 130 -- ns tLLWL 200 300 3tCLCL - 50 3tCLCL + 50 ns tAVDV -- 585 -- 9tCLCL - 165 ns tLLDV -- 516 -- 8tCLCL - 150 ns tRHDZ -- 96 -- 2tCLCL - 70 ns tRHDX 0 -- 0 -- ns tRLRH tWLWH tRLDV 400 400 -- -- -- 251 6tCLCL - 100 6tCLCL - 100 -- -- -- 5tCLCL - 165 ns ns ns tLLAX 48 -- 1tCLCL - 35 -- ns tCLCL tLHLL tAVLL -- 126 43 Max. -- -- -- See Guaranteed Operating Range Min. 62.5 2tCLCL - 40 1tCLCL - 40 Max. -- -- -- ns ns ns Unit
30/38
Semiconductor External Data Memory Access AC Characteristics 2
MSM80C31F/80C51F
(VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = -40C to +85C; load capacitance for Port 0, ALE, and PSEN = 100 pF ; load capacitance for all other outputs = 80 pF)
Variable Clock Parameter Symbol 12 MHz Clock Min. XTAL1, XTAL2 Oscillation Cycle ALE Single Width Adderss Setup Time (to ALE Falling Edge) Adderss Hold Time (from ALE Falling Edge) RD Single Width WR Single Width RAM Data Read Time (from RD Single Falling Edge) RAM Data Read Hold Time (from RD Single Rising Edge) Data Bus Floating Time (from RD Single Rising Edge) RAM Data Read Time (from ALE Single Falling Edge) RAM Data Read Time (from Address Output) RD/WR Output Time from ALE Falling Edge RD/WR Output Time from Address Output RD Output Time from Data Output Time from Data Output to WR Rising Edge Data Hold Time (WR Rising Edge) Time from RD Output to Address Float Time from RD/WR Rising Edge to ALE Rising Edge tWHLH 43 183 1tCLCL - 40 1tCLCL + 100 ns tWHQX tRLAZ 33 -- -- 0 1tCLCL - 50 -- -- 0 ns ns tQVWX tQVWH 23 433 -- -- 1tCLCL - 60 7tCLCL - 150 -- -- ns ns tAVWL 203 -- 4tCLCL - 130 -- ns tLLWL 150 300 3tCLCL - 100 3tCLCL + 50 ns tAVDV -- 585 -- 9tCLCL - 165 ns tLLDV -- 516 -- 8tCLCL - 150 ns tRHDZ -- 96 -- 2tCLCL - 70 ns tRHDX 0 -- 0 -- ns tRLRH tWLWH tRLDV 400 400 -- -- -- 251 6tCLCL - 100 6tCLCL - 100 -- -- -- 5tCLCL - 165 ns ns ns tLLAX 48 -- 1tCLCL - 35 -- ns tCLCL tLHLL tAVLL -- 126 43 Max. -- -- -- See Guaranteed Operating Range Min. 62.5 2tCLCL - 40 1tCLCL - 40 Max. -- -- -- ns ns ns Unit
31/38
Semiconductor External Data Memory Read Cycle
tLHLL ALE
MSM80C31F/80C51F
tWHLH
PSEN tLLDV tLLWL RD
tAVLL t t LLAX RLAZ
tRHDZ
tRLRH
tRLDV
tRHDX A0~A7 PCL
PORT 0
INSTR IN
A0~A7 PCL
A0~A7 Rr or DPL
tAVWL PORT 2 PCH A8~A15 PCH
tAVDV A8~A15 PCH
P2.0~P2.7 DATA or A8~A15 DPH
External Data Memory Write Cycle
tLHLL ALE tWHLH
PSEN tLLWL WR
tAVLL
tLLAX tQVWX
tWLWH
tQVWH
tWHQX A0~A7 PCL
PORT 0
INSTR IN
A0~A7 PCL
A0~A7 Rr or DPL
DATA (ACC)
tAVWL PORT 2
A8~A15 PCH
A8~A15 PCH
P2.0~P2.7 DATA or A8~A15 DPH
A8~A15 PCH
32/38
Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 1
(Ta = -40C to +85C ; VCC = 5 V 20% ; VSS = 0 V) Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Min. 12tCLCL 10tCLCL - 133 2tCLCL - 117 0 -- Max. -- -- -- -- 10tCLCL - 133 Unit ns ns ns ns ns
MACHINE CYCLE ALE
0
1
2
3
4
5
6
7
8
tXLXL SHIFT CLOCK tQVXH OUTPUT DATA
0
tXHQX
1
2
3
4
5
6
7
tXHDV INPUT DATA
VALID VALID
tXHDX
VALID VALID VALID VALID VALID VALID
33/38
Semiconductor
MSM80C31F/80C51F
Serial Port Timing (I/O Expansion Mode) AC Characteristics 2
(Ta = -40C to +85C ; VC C =2.5 to 4.0 V ; VSS = 0 V) Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Min. 12tCLCL 10tCLCL - 133 2tCLCL - 117 0 -- Max. -- -- -- -- 10tCLCL - 133 Unit ns ns ns ns ns
MACHINE CYCLE ALE
0
1
2
3
4
5
6
7
8
tXLXL SHIFT CLOCK tQVXH OUTPUT DATA
0
tXHQX
1
2
3
4
5
6
7
tXHDV INPUT DATA
VALID VALID
tXHDX
VALID VALID VALID VALID VALID VALID
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Semiconductor
MSM80C31F/80C51F
AC Characteristics Measuring Conditions Input/output signal
VOH VIH TEST POINT VOL VIL VIL VOL VIH VOH
*
The input signals in AC test mode are either VOH (logic "1") or VOL (logic "0") input signals where logic "1" corresponds to a CPU output signal waveform measuring point in excess of VIH, and logic "0" to a point below VIL.
Floating
Floating VOH VIH VIL VIH VIL VOH
VOL
VOL
*
The port 0 floating interval is measured from the time the port 0 pin voltage drops below VIH after sinking to GND at 2.4 mA when switching to floating status from a "1" output, and from the time the port 0 pin voltage exceeds VIL after connecting to a 400 mA source when switching to floating status from a "0" output.
XTAL1 External Clock Input Waveform Conditions
Variable Clock Parameter External Clock Frequency High Time Low Time Rise Time Fall Time Symbol 1/tCLCL tCHCX tCLCX tCLCH tCHCL DC 20 20 -- -- See Guaranteed Operating Range Min. Max. 16 -- -- 20 20 Unit MHz ns ns ns ns
External clock waveform
VCC - 0.5 0.45 V 0.7VCC 0.2VCC - 0.1 tCHCX
tCHCL tCLCH
tCLCX
tCLCL
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Semiconductor
MSM80C31F/80C51F
PACKAGE DIMENSIONS
(Unit : mm)
DIP40-P-600-2.54
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 6.10 TYP.
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Semiconductor
MSM80C31F/80C51F
(Unit : mm) QFP44-P-910-0.80-2K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.41 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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Semiconductor
MSM80C31F/80C51F
(Unit : mm)
QFJ44-P-S650-1.27
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 2.00 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1995 Oki Electric Industry Co., Ltd.
Printed in Japan

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